A shortened time to market, often limits the amount of product testing that can be performed. Microprocessor-based products released with unstable memory may experience only intermittent failures, but even those can lead to a costly recall. To minimize that risk, comprehensive memory timing analysis need to be performed during the design phase of the product.
Net topologies, trace impedances and terminations play an important role in waveform integrity. Trace length, vias and cross talk play an important role in timing.. A combined signal integrity analysis and timing analysis environment is needed to guarantee proper function of the DDR interface.
JEDEC timing requirements
In the JESD79 and JESD208 documents, more information can be found about the different DDRx specification.
Thorough knowledge of the different timing parameters within a DDRx device is mandatory for performing detailed accurate timing analysis.
By using high-speed design, analysis and verification techniques early in the design cycle, designers can eliminate layout iterations and ensure that products are marketed on time.